Objective To obtain a challenging position as a Software Engineer.
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Summary
· 5+ years of experience in the Telecom/Datacom industry developing Embedded Software.
· Worked as an Embedded Software Engineer (VOIP Group) for Telica, a Telecom Start-up.
· Worked on Gigabit Ethernet Card for Telica’s Media Gateway.
· Worked on Alcatel’s Edge router division, formerly known as NewBridge Networks.
· Worked as an Embedded Software Engineer in Future Software on MPLS, IP, RIP.
· Proven track record of delivering projects on time in a Start-up environment.

Education B.E. in Computer Science, Regional Engineering College - Trichy, India - 1998.

Skills Languages: C/C++, PowerPC Assembly, 8031 Assembly, FORTRAN and Prolog.
Processors: PowerPC (MPC8260, MPC7410), INTEL i-960, 8031 MC.
Operating Systems: VxWorks, pSOS, LYNX, Linux, DG UNIX, Win NT.
Environments Tools: ADTECH and SmartBits traffic generators, CSRCS, CVS and Clear Case
for Version control, BugZilla bugs tracking, Analyzers for ATM, BCG
(Bulk Call Generator), Sage, Hammer, Adtran, ATM Sniffers,
Codewright, Source Insight, EMACS and VIM for code editing), LUMOS
TL-1 (Transaction Language –1) agent, CLI, Go-Ahead library, high
availability architecture, tcl/tk script.
Protocols: TCP/IP, MPLS, Routing Protocols RIP, ATM, FR, SONET/SDH, ARP,
SNMP, Diff-Serv, Inverse ARP for ATM, MPOA, LANE, NPPC
(Network Program To Program Communication, a Transport Layer
Protocol), LLC-SNAP (RFC 1483), ICMP, HSRP, VRRP, IEEE 802.3,
IEEE 802.2, IEEE 8-2.1p/q, IEEE 802.11,LDP and CRLDP.

Projects Embedded Software Engineer - Telica, Marlborough MA July 2001 – Till date

Gigabit Ethernet/ATM Host and IO Modules
Designed, developed, tested and successfully delivered all the Embedded Provisioning Software on a Gigabit Ethernet IO Module and Host module for the Plexus 9000 VOIP and VOATM Media Gateway. Worked diligently for the success of the project in every stage of the Product Life-Cycle from design to delivery and deployment in customer network.

· Designed a Redundancy model for Host module and IO module.
· Designed and implemented Gigabit Ethernet ports configuration commands using LUMOS TL-1 agent for DIX II and IEEE 802.3 with IEEE 803.2 support.
· Implemented support for IEEE 802.1p/q.
· Implemented a mechanism for Routing RTP traffic from the Voice Processor Card to the Gig-E Card through the ATM switch fabric using Lucent APC (ATM Port Controller) chips.
· Implemented Dynamic Bandwidth Mgmt for the Gigabit Ethernet IOM.
· Developed a Network Gig-E Redundancy Solution working with CISCO Systems Engineers using HSRP protocol.
· Designed an ENAIOM process for configuring ARP, Ping and Gig-E drivers.
· Worked with LYNX OS kernel and Ethernet device drivers for various interfaces.
· Designed and developed Gigabit Ethernet Device Drivers to program the MACs and PHYs.
· Worked with device drivers to handle various interrupts through ISR.
· Developed Gig-E Power On Self-Tests.
· Implemented Ping and TraceRoute utilities for trouble-shooting through the TL-1 agent.
· Implemented Static Route support on the Gig-E and ATM card through Tl-1 agent.
· Developed OAM support for Layers 1, 2 3 on the Gig-E and ATM card.
· Configured the Packet Forwarding Engine FPGA to forward RTP traffic on Gig-E.
· Developed mechanism for maintaining the Heartbeat with all the processes on Gig-E and ATM card.
· Performed ATM card testing with Marconi ATM switch and Alcatel 7640 router using tcl/tk scripts.
· Performed Interoperability testing with Extreme, CISCO and Riverstone routers.
· Performed Bearer path testing, Voice quality testing and Fail-over testing on this test bed with SAGE and HAMMER.
· Achieved each of the above goals under severe time-pressure by working start-up hours.

Gig-E Host module
Designed and implemented on the Gig-E host module. Host module writes the entire port configuration to the XML database. In case of host failure standby host reads the XML database and then it audits the IOM. A successful fail-over is reported if none of the audit fails.

Gig-E IOM Module
Gig-E IOM module interfaced with Device drivers thru IOCTL calls for Intel IXF1002 IXF440 Gigabit Ethernet MAC chips and the Marvell 88E1041 PHY chip. The driver configures the IOM in to Quad GigE Copper, Quad GigE Fiber or Octal 10/100 mode, depending on the rear-card. (PCI bus) (LynxOS-MPC7410). Gig-E was responsible for configuring FPGA, ARP, PING drivers on the card.

Software Engineer - Alcatel Edge Service Router 7420, Andover- MA Apr 2000 - July 2001

Worked on ATM/FR/MPLS/Diff-Serv/ modules of the router
· Involved in the design, development and testing of ATM/FR/Diff-Serv/Bandwidth Manager modules which included.
· Implemented new CLI commands in ATM/FR/Diff-Serv/Bandwidth Manager modules.
· Involved in the design to support AF/EF PHB (Per Hop Behavior) groups.
· Involved in designing traffic policies for defining a) Classification b) Marking c) Policing d) Queuing Behaviour.
· Ported support for Netplane Systems LTCS (MPLS) code in ATM module.
· Implemented support for NBMA interfaces in ATM module
· Integrated Netplane Systems (formerly HJ) IPOA with ATM module
· Conducted unit testing and system testing with Cisco routers.
· Conducted interoperability testing with Cisco routers.

Senior Software Engineer MPLS -LDP (Label Distribution Protocol)-VC Merging, Future
Software Pvt. Ltd., Madras, India – June-1999- Jan 2000

Worked on MPLS
· Designed the upstream control block state event machine for DoD (Downstream on Demand) in Ordered control mode and DU (Downstream Unsolicited) Ordered control mode.
· Implemented Downstream on demand in ordered control mode for VC-Merge nodes in MPLS (Multi Protocol Label Switching) Domain.
· Conducted Interoperability testing between VC Merge Nodes and Non VC-Merge Nodes.
· Implemented Down Stream Unsolicited in ordered control mode for VC Merge nodes in MPLS domain.
· Conducted integration testing for Huawei Technologies, China.
· Conducted system testing on Cisco routers.

Software Engineer -LLC-CM- LLC/SNAP-Connection Management for MPOA and
LANE, Future Software Pvt. Ltd., Madras, India Oct 1998 - May 1999

· Implemented the support for LLC/SNAP encapsulation technique (RFC 1483) for multiplexing higher layer Protocol entities like (LANE, MPOA, IPOA etc) to interface with the UNI signaling layer.
· Designed Connection Management scheme for maintaining the VCs and tearing down the VCs through Finite State Event machine.
· Conducted Unit testing of the new modules.
· Conducted integration testing with MPOA.
· Conducted Unit testing and integration testing for HP, Japan.

Software Engineer -Enhancement Future IP/RIP (ROUTER), Future Software Pvt. Ltd.,
Madras, India – May 1998 – Oct 1998

· Implemented static routes support.
· Worked on the Future Software IP stack.
· Worked with SNMP for managing IP/RIP.
· Conducted Unit testing and System testing of RIP protocol with Cisco routers.

Design and Implementation of CREW (CONCURRENT READ EXCLUSIVE
WRITE) semantic in collaborative and fault tolerant Environment, R.E.C. (Regional
Engineering College) Trichy, Tamil Nadu India – June 1997 – Dec 1997

· Designed and implemented the multi-user file editing system in client server environment.
· Implemented NPPC protocol for communication between the server and clients.
· Designed the system to be Fault tolerant by deploying the backup server.
· Worked with Unix internals and socket layer programming.